The invention relates to a fast-access monolithic integrated data storage circuit on a semi-insulating substrate.
A fast-access data storage circuit is described in "IEEE Transactions on Electron Devices", Vol. ED-33, No. 1, January 1986, pages 104 to 110. A last circuit of this kind is constructed as a matrix of memory points which are interconnected by means of interconnection lines. The matrix of memory points is divided in two in order to divide the length of these access lines to the memory points in two, thus reducing the signal propagation time approximately by a factor 4. With an access line there are associated a resistor R and a capacitor C, both of which depend on the length of the line, so that the time constant RC is substantially a function of the square of the length; thus, by dividing the length of the line by 2, the propagation time is divided by 4. The propagation time could thus be further reduced by a few orders of magnitude by dividing the matrix of memory points, for example, into four sections, but this method is not satisfactory in the case of ultrafast data signals, for example, in the case of applications involving a super-computer operating at speeds in the order of from 100 to 1000 MIPS (Mega Instructions Per Second). A major drawback of the use of such a method is that the propagation time is no longer negligibly small with respect to the positive-going edge of the signals which are subject to a delay, are distorted and are no longer reproduced so as to be identical on the output of the circuit.